Scalable two-stage virtual output queuing switch and method of operation

ABSTRACT

A fixed-size data packet switch comprising: 1) N input ports for receiving incoming fixed-size data packets at a first data rate and outputting the fixed-size data packets at the first data rate; 2) N output ports for receiving fixed-size data packets at the first data rate and outputting the fixed-size data packets at the first data rate; and 3) a switch fabric interconnecting the N input ports and the N output ports. The switch fabric comprises: a) N input buffers for receiving incoming fixed-size data packets at the first data rate and outputting the fixed-size data packets at a second data rate equal to at least twice the first data rate; b) N output buffers for receiving fixed-size data packets at the second data rate and outputting the fixed-size data packets at the first data rate; and c) a bufferless, non-blocking interconnecting network for receiving from the N input buffers the fixed-size data packets at the second data rate and transferring the fixed-size data packets to the N output buffers at the second data rate.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present invention is related to those disclosed in U.S.patent application Ser. No. [Docket No. 01-HK-035], filed concurrentlyherewith, entitled “APPARATUS FOR SWITCHING DATA IN HIGH-SPEED NETWORKSAND METHOD OF OPERATION”. Application Ser. No. {Docket No. 01-HK-035] iscommonly assigned to the assignee of the present invention. Thedisclosure of the related patent application is hereby incorporated byreference for all purposes as if fully set forth herein.

TECHNICAL FIELD OF THE INVENTION

[0002] The present invention is generally directed to packet switchingnetworks and, more specifically, to a switch having a bufferless,non-blocking interconnecting network and internal speed-up buffers.

BACKGROUND OF THE INVENTION

[0003] Packet switching involves the transmission of data in packetsthrough a data network. Fixed sized packets are referred to as cells.Each block of end-user data that is to be transmitted is divided intocells. A unique identifier, a sequence number and a destination addressare attached to each cell. The cells are independent and may traversethe data network by different routes. The cells may incur differentlevels of propagation delay, or latency, caused by physical paths ofdifferent length. The cells may be held for varying amounts of delaytime in buffers in intermediate switches in the network. The cells alsomay be switched through different numbers of packet switches as thecells traverse the network, and the switches may have unequal processingdelays caused by error detection and correction.

[0004] Historically, a bufferless crossbar has been used as theswitching fabric of a virtual output queue (VOQ) switch, which suffersfrom the scheduling bottleneck that limits the switch's scalability. Ithas been shown that the scheduling bottleneck can be overcome byreplacing the bufferless crossbar with an internally buffered crossbar(IBX), where a small size buffer is located at each crosspoint of theinternally buffered crossbar (VOQ+IBX). Specifically, it has been shownthat for each internal buffer, a size as small as two cells (or packets)can bring at least two benefits: (1) the ability to perform thescheduling task by each input/output arbiter independently; and (2) theability to achieve a theoretically guaranteed 100% throughput under anyadmissible traffic load, with each input or output having an arbitrationcomplexity of O(Log N) per time slot, for an N×N switch.

[0005] However, as the switch size grows, the number of internal buffersincreases quadratically, resulting in greater difficulties in theimplementation of the buffered crossbar. Thus, the physical scalabilityof a buffered crossbar using current silicon technology is limited.Therefore, there is a need in the art for improved fixed-sized packetswitches. In particular, there is a need for a highly scalable switcharchitecture having a bufferless, non-blocking interconnecting networkbetween the input ports and the output ports of the switch. Moreparticularly, there is a need for a switch that does not require the useof a crossbar containing internal buffers.

SUMMARY OF THE INVENTION

[0006] The present invention comprises a novel switch architecturecapable of achieving performances similar to a virtual output queue withinternally buffered crossbar (VOQ+IBX) switch, but without the need ofan internal buffer at each crosspoint of the switching fabric. A novelscalable virtual output queue and combined input and output queuing(VOQ+CIOQ) switch architecture achieves the optimal balance between theadvantages and disadvantages of a speed-up of two combined input andoutput queuing (CIOQ) switches and a buffered crossbarvirtual-output-queue (VOQ) switches.

[0007] To address the above-discussed deficiencies of the prior art, itis a primary object of the present invention to provide a fixed-sizedata packet switch. According to an advantageous embodiment of thepresent invention, the fixed-size data packet switch comprises: 1) Ninput ports capable of receiving incoming fixed-size data packets at afirst data rate and outputting the fixed-size data packets at the firstdata rate; 2) N output ports capable of receiving fixed-size datapackets at the first data rate and outputting the fixed-size datapackets at the first data rate; and 3) a switch fabric interconnectingthe N input ports and the N output ports. The switch fabric comprises:a) N input buffers capable of receiving incoming fixed-size data packetsat the first data rate and outputting the fixed-size data packets at asecond data rate equal to at least twice the first data rate; b) Noutput buffers capable of receiving fixed-size data packets at thesecond data rate and outputting the fixed-size data packets at the firstdata rate; and c) a bufferless, non-blocking interconnecting networkthat receives from the N input buffers the fixed-size data packets atthe second data rate and transferring the fixed-size data packets to theN output buffers at the second data rate.

[0008] According to one embodiment of the present invention, thebufferless, non-blocking interconnecting network comprises a bufferlesscrossbar.

[0009] According to another embodiment of the present invention, each ofthe N input buffers is at least twice the size of each of the N outputbuffers.

[0010] According to still another embodiment of the present invention,the fixed-size data packet switch further comprises a schedulingcontroller capable of scheduling transfer of the fixed-size data packetsfrom the N input ports to the switch fabric.

[0011] According to yet another embodiment of the present invention, thescheduling controller is capable of scheduling transfer of thefixed-size data packets from the N output ports to an external device.

[0012] According to a further embodiment of the present invention, thescheduling controller is capable of scheduling transfer of thefixed-size data packets from the N input buffers to the bufferless,non-blocking interconnecting network.

[0013] According to a still further embodiment of the present invention,the scheduling controller is capable of scheduling transfer of thefixed-size data packets from the N output buffers to the N output ports.

[0014] The foregoing has outlined rather broadly the features andtechnical advantages of the present invention so that those skilled inthe art may better understand the detailed description of the inventionthat follows. Additional features and advantages of the invention willbe described hereinafter that form the subject of the claims of theinvention. Those skilled in the art should appreciate that they mayreadily use the conception and the specific embodiment disclosed as abasis for modifying or designing other structures for carrying out thesame purposes of the present invention. Those skilled in the art shouldalso realize that such equivalent constructions do not depart from thespirit and scope of the invention in its broadest form.

[0015] Before undertaking the DETAILED DESCRIPTION OF THE INVENTIONbelow, it may be advantageous to set forth definitions of certain wordsand phrases used throughout this patent document: the terms “include”and “comprise”, as well as derivatives thereof, mean “inclusion withoutlimitation;” the term “or,” is inclusive, meaning “and/or;” the phrases“associated with” and “associated therewith,” as well as derivativesthereof, may mean “include,” “be included within,” “interconnect with,”“contain,” “be contained within,” “connect to or with”, “couple to orwith,” “be communicable with,” “cooperate with,” “interleave,”“juxtapose,” “be proximate to,” “be bound to or with,” “have,” “have aproperty all of,” or the like; and the term “controller” includes anydevice, system or part thereof that controls at least one operation,such a device may be implemented in hardware, firmware or software, orsome combination of at least two of the same. In particular, acontroller may comprise a data processor and an associated memory thatstores instructions that may be executed by the data processor. Itshould be noted that the functionality associated with any particularcontroller may be centralized or distributed, whether locally orremotely. Definitions for certain words and phrases are providedthroughout this patent document, those of ordinary skill in the artshould understand that in many, if not most instances, such definitionsapply to prior, as well as future uses of such defined words andphrases.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] For a more complete understanding of the present invention, andthe advantages thereof, reference is now made to the followingdescriptions taken in conjunction with the accompanying drawings,wherein like numbers designate like objects, and in which:

[0017]FIG. 1 illustrates an exemplary packet switching networkcontaining packet switches in accordance with the principles of thepresent invention;

[0018]FIG. 2 illustrates in greater detail selected portions of anexemplary packet switch in FIG. 1 according to one embodiment of thepresent invention;

[0019]FIG. 3 illustrates in greater detail selected portions of theswitching fabric in the exemplary packet switch according to oneembodiment of the present invention; and

[0020]FIG. 4 is a flow chart illustrating the operation of the exemplarypacket switch according to one embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0021]FIGS. 1 through 4, discussed below, and the various embodimentsused to describe the principles of the present invention in this patentdocument are by way of illustration only and should not be construed inany way so as to limit the scope of the invention. Those skilled in theart will understand that the principles of the present invention may beimplemented in any suitably arranged fixed-size packet data switch.

[0022]FIG. 1 illustrates an exemplary packet switching network 100containing packet switches 111-114 in accordance with the principles ofthe present invention. Packet switching network 100 contains asubnetwork 105, indicated by a dotted line, comprising packet switches111-114, that interconnects end-user devices 131-134 with each other andwith other switches (not shown) and other end-user devices (not shown)associated with packet switching network 100. Packet switches 111-114are interconnected by data links 121-126. Subnetwork 105 is intended tobe a representative portion of packet switching network 100, which maycontain many other redundant packet switches similar to packet switches111-114.

[0023] End-user devices 131-134 each may comprise any commonly knownprocessing device, such as a telephone, a personal computer (PC), a faxmachine, an office LAN, a network server, or the like, that maycommunicate via a packet switching network. For example, end-user 131may comprise a remote network server that is sending a data file toend-user 133, which is a desktop PC. The data file that is to betransmitted is segmented into fixed-size data packets (or cells) inend-user 131. An identifier for the data transfer is appended to eachdata cell. A sequence number is also appended to each data cell, as is adestination address associated with end-user 133.

[0024] Next, the data cells are transferred to packet switch 111. Packetswitch 111 may transfer the data cells to end-user 133 by severalphysical paths. For example, packet switch 111 may send the data cellsdirectly to packet switch 114 across data link 126. If the data trafficload on data link 126 is heavy, packet switch 111 may send some or allof the data cells indirectly to packet switch 114 via data link 121,packet switch 112, and data link 122. Alternatively, packet switch 111may send some or all of the data cells indirectly to packet switch 114via data link 124, packet switch 113, and data link 123. Packet switch114 transfers the data cells to end user device 133, which uses theidentifier information and the sequence numbers from each data cell toreassemble the original data file sent by end-user device 131.

[0025]FIG. 2 illustrates in greater detail selected portions ofexemplary packet switch 111 according to one embodiment of the presentinvention. Packet switch 111 comprises N input ports 210, N output ports220, switch fabric 230, and scheduling controller 240. N input ports 210include exemplary input ports 210A, 210B, and 210C, which arearbitrarily labeled Input Port 1, Input Port 2, and Input Port N,respectively. N output ports 220 include exemplary output ports 220A,220B, and 220C, which are arbitrarily labeled Output Port 1, Output Port2, and Output Port N, respectively.

[0026] Cells arrive on N input data paths, including exemplary inputdata path 1 (IDP1), input data path 2 (IDP2), and input data path N(IDPn), and are buffered in the N input ports 210. The buffered cellsare transferred under the control of scheduling controller 240 to switchfabric 230 over N input speed-up data paths, including exemplary inputspeed-up data path 1 (ISUDP1), input speed-up data path 2 (ISUDP2), andinput speed-up data path N (ISUDPn). The switched cells are transferredunder the control of scheduling controller 240 from switch fabric 230 toN output ports 220 over N output speed-up data paths, includingexemplary output speed-up data path 1 (OSUDP1), output speed-up datapath 2 (OSUDP2), and output speed-up data path N (OSUDPn).

[0027] As noted above, the present invention comprises a novel switcharchitecture that achieves performances similar to a virtual outputqueue with an internally buffered crossbar (VOQ+IBX) switch, but withoutthe need of an internal buffer at each crosspoint of the switchingfabric. Accordingly, switch fabric 230 is a bufferless, non-blockinginterconnecting network with internal speed-up buffers that provides anovel scalable architecture. In an exemplary embodiment, switch fabric230 is a bufferless crossbar that operates with small, speed-up-of-twoinput and output buffers to achieve the performance of a bufferedcrossbar without using an internal buffer at each crosspoint of theswitching fabric.

[0028]FIG. 3 illustrates in greater detail selected portions ofswitching fabric 230 in exemplary packet switch 111 according to oneembodiment of the present invention. Switching fabric 230 comprises Ninternal speed-up-of-two input buffers (2×), bufferless crossbar 340,and N internal speed-up-two output buffers (2×). The N internalspeed-up-of-two input buffers include exemplary input buffers 321, 322and 323. The N internal speed-up-of-two output buffers include exemplaryoutput buffers 331, 332, and 333.

[0029] Cells arrive from the input ports at a speed of 1× (e.g., 10Mbps) on N input speed-up data paths, including ISUDP1, ISUDP2, andISUDPn, and are buffered in input buffers 321-323. The buffered cellsare transferred at a higher speed of 2× (e.g., 20 Mbps) under thecontrol of scheduling controller 240 to bufferless crossbar 340 over Ninput speed-up-of-two data paths. The switched cells are transferredunder the control of scheduling controller 240 from bufferless crossbar340 to N output buffers at a speed of 2× over N output speed-up-of-twodata paths. Finally, the buffered cells are transferred under thecontrol of scheduling controller 240 from the N output buffers to the Noutput ports at a speed of 1× over N output speed-up data paths,including OSUDP1, OSUDP2, and OSUDPm.

[0030] The present invention emulates a buffered crossbar by a combinedinput and output queue (CIOQ) switch where each input/output bufferoperates in an internal speed-up of two and a bufferless non-blockinginterconnecting network, such as bufferless crossbar 340, is used as theswitching fabric. As noted, there are two kinds of buffers in switch111: the speed-up of one buffers (i.e., input ports 210), used asexternal input buffers, and the speed-up of two buffers, used asinternal input buffers 321-323 and as internal output buffers 331-333.

[0031] The speed-up-of-one (1×) input buffers (i.e., input ports 210)provide buffers for queuing cells, whereas the speed-up-of-two (2×)input and output buffers enable the emulation of a buffered crossbar.The size requirements for each speed-up of two input and output bufferare 2N and N cells, respectively. The input buffer at each input portgenerally requires a large space and must be located outside thespeed-up of two switching fabric. Queuing at each external/internalinput buffer is a virtual output queue (VOQ) where cells/packets arequeued according to their destined output ports, and at each internaloutput buffer may be, for example, a first-in, first-out (FIFO)register.

[0032] The proposed switch architecture is optimal in the sense that itinherits two distinct advantages exclusively held by the VOQ switcheswith either a bufferless or buffered crossbar as the switching fabric,i.e., the low individual buffer bandwidth requirement of the former andthe good achievable performances of the latter.

[0033] Scheduling by scheduling controller 240 consists of two tasks: 1)scheduling the forwarding of cells from the N external input buffers(i.e., input ports 210) to the internal input buffers (i.e., inputbuffers 321-323); and (2) scheduling the switching of cells in internalinput buffers 321-323 to internal output buffers 331-333. In principle,the CIOQ is controlled by the scheduling controller 240 to simulate aninternally buffered crossbar (IBX). It is not required to be an exactsimulation, but the delay discrepancy is tightly upper bounded by 2Nslots. This can be done because, in a VOQ+IBX switch, there are at mostT cells transmitted or received by an input or output port over any timeinterval of T slots.

[0034]FIG. 4 depicts flow chart 400, which illustrates the operation ofexemplary packet switch 111 according to one embodiment of the presentinvention. During input scheduling, a cell is forwarded to thecorresponding one of internal input buffers 321-323 if it would beforwarded to the an internally buffered crossbar (IBX) in the simulatedswitch (process step 405). During output scheduling, each cell is markedat its internal input buffer in the CIOQ as being active if it isselected by its destined output in the simulated switch to betransmitted out (process step 410). Switch 111 repeats steps 405 and 410N times, once per time slot (process step 415). Next, switch 111 finds amaximal matching of inputs and outputs over all active cells currentlyqueued at the internal input buffers of the CIOQ (process step 420).Switch 111 then configures bufferless crossbar 340 according to thecurrent matching (process step 425) and transmits the matched head ofline (HOL) cell at each VOQ (process step 430). Switch 111 then repeatsstep 420, 425 and 430 2N times, twice per time slot (i.e., speed-up oftwo) (process step 435).

[0035] In the above algorithm, steps 405, 410, and 415 are pipelinedwith steps 420, 425, 430 and 435 in a cycle period of N slots. A maximumsize matching or a stable matching can be used instead at step 420,resulting in a slowdown of step 435 from the speed-up of two to thespeed-up of one, or an exact emulation of a VOQ+IBX switch,respectively. However, finding a maximum size matching or a stablematching are generally prohibited, in practice, because of their largecomplexities of O(N^(2.5)) and ω(N²), respectively.

[0036] It is not difficult to see that the space requirements for eachinternal input and output buffer are 2N and N. In the internal inputbuffer, there are, in a cycle of N time slots, at most N new arrivingcells at one of internal buffers 321-333. Additionally, there may be atmost N cells that have already been queued at the buffer at thebeginning of this cycle. As a result, at most 2N cells are needed perinternal input buffer.

[0037] In the internal output buffer, there are, in a cycle of N timeslots, at most N arriving cells, coming at a rate of at most two persingle time slot. In addition, there are at most N/2 cells queuing at aninternal output buffer at the beginning of a cycle. Therefore, N cellsare enough for each internal output buffer. Since the switch performance(in terms of delay, jitter, throughput, fairness and the like) ishandled by the emulation of a VOQ+IBX switch performed by steps 405,410, and 415, the maximal matching algorithm can be implemented in anyway that could be very hardware simple. Generally, finding a maximalmatching requires a centralized process with a worst case iterationnumber of N and a complexity of O(N^ 2).

[0038] Although the present invention has been described in detail,those skilled in the art should understand that they can make variouschanges, substitutions and alterations herein without departing from thespirit and scope of the invention in its broadest form.

What is claimed is:
 1. For use in a fixed-size packet switch, a switchfabric comprising: N input buffers capable of receiving incomingfixed-size data packets at a first data rate and outputting saidfixed-size data packets at a second data rate equal to at least twicesaid first data rate; N output buffers capable of receiving fixed-sizedata packets at said second data rate and outputting said fixed-sizedata packets at said first data rate; and a bufferless, non-blockinginterconnecting network capable of receiving from said N input bufferssaid fixed-size data packets at said second data rate and transferringsaid fixed-size data packets to said N output buffers at said seconddata rate.
 2. The switch fabric as set forth in claim 1 wherein saidbufferless, non-blocking interconnecting network comprises a bufferlesscrossbar.
 3. The switch fabric as set forth in claim 1 wherein each ofsaid N input buffers is at least twice the size of each of said N outputbuffers.
 4. A method of operating a switch fabric in a fixed-size packetswitch, the method comprising the steps of: storing incoming fixed-sizedata packets in N input buffers at a first data rate; outputting thefixed-size data packets from the N input buffers at a second data rateequal to at least twice the first data rate; transferring the fixed-sizedata packets output by the N input buffers at the second data ratethrough a bufferless, non-blocking interconnecting network to N outputbuffers; storing the fixed-size data packets transferred through thebufferless, non-blocking interconnecting network in the N output buffersat the second data rate; and outputting the fixed-size data packets fromthe n output buffers at the first data rate.
 5. The method as set forthin claim 4 wherein the bufferless, non-blocking interconnecting networkcomprises a bufferless crossbar.
 6. The method as set forth in claim 5wherein each of the N input buffers is at least twice the size of eachof the N output buffers.
 7. A fixed-size data packet switch comprising:N input ports capable of receiving incoming fixed-size data packets at afirst data rate and outputting said fixed-size data packets at saidfirst data rate; N output ports capable of receiving fixed-size datapackets at said first data rate and outputting said fixed-size datapackets at said first data rate; and a switch fabric interconnectingsaid N input ports and said N output ports comprising: N input bufferscapable of receiving incoming fixed-size data packets at said first datarate and outputting said fixed-size data packets at a second data rateequal to at least twice said first data rate; N output buffers capableof receiving fixed-size data packets at said second data rate andoutputting said fixed-size data packets at said first data rate; and abufferless, non-blocking interconnecting network capable of receivingfrom said N input buffers said fixed-size data packets at said seconddata rate and transferring said fixed-size data packets to said N outputbuffers at said second data rate.
 8. The fixed-size data packet switchas set forth in claim 7 wherein said bufferless, non-blockinginterconnecting network comprises a bufferless crossbar.
 9. Thefixed-size data packet switch as set forth in claim 7 wherein each ofsaid N input buffers is at least twice the size of each of said N outputbuffers.
 10. The fixed-size data packet switch as set forth in claim 7further comprising a scheduling controller capable of schedulingtransfer of said fixed-size data packets from said N input ports to saidswitch fabric.
 11. The fixed-size data packet switch as set forth inclaim 10 wherein said scheduling controller is capable of schedulingtransfer of said fixed-size data packets from said N output ports to anexternal device.
 12. The fixed-size data packet switch as set forth inclaim 10 wherein said scheduling controller is capable of schedulingtransfer of said fixed-size data packets from said N input buffers tosaid bufferless, non-blocking interconnecting network.
 13. Thefixed-size data packet switch as set forth in claim 12 wherein saidscheduling controller is capable of scheduling transfer of saidfixed-size data packets from said N output buffers to said N outputports.
 14. A communication network capable of transferring data infixed-size packets between a plurality of end-user devices, saidcommunication network comprising: a plurality of fixed-size data packetswitches, at least one of said fixed-size data packet switchescomprising: N input ports capable of receiving incoming fixed-size datapackets at a first data rate and outputting said fixed-size data packetsat said first data rate; N output ports capable of receiving fixed-sizedata packets at said first data rate and outputting said fixed-size datapackets at said first data rate; and a switch fabric interconnectingsaid N input ports and said N output ports comprising: N input bufferscapable of receiving incoming fixed-size data packets at said first datarate and outputting said fixed-size data packets at a second data rateequal to at least twice said first data rate; N output buffers capableof receiving fixed-size data packets at said second data rate andoutputting said fixed-size data packets at said first data rate; and abufferless, non-blocking interconnecting network capable of receivingfrom said N input buffers said fixed-size data packets at said seconddata rate and transferring said fixed-size data packets to said N outputbuffers at said second data rate.
 15. The communication network as setforth in claim 14 wherein said bufferless, non-blocking interconnectingnetwork comprises a bufferless crossbar.
 16. The communication networkas set forth in claim 14 wherein each of said N input buffers is atleast twice the size of each of said N output buffers.
 17. Thecommunication network as set forth in claim 14 further comprising ascheduling controller capable of scheduling transfer of said fixed-sizedata packets from said N input ports to said switch fabric.
 18. Thecommunication network as set forth in claim 17 wherein said schedulingcontroller is capable of scheduling transfer of said fixed-size datapackets from said N output ports to an external device.
 19. Thecommunication network as set forth in claim 17 wherein said schedulingcontroller is capable of scheduling transfer of said fixed-size datapackets from said N input buffers to said bufferless, non-blockinginterconnecting network.
 20. The communication network as set forth inclaim 19 wherein said scheduling controller is capable of schedulingtransfer of said fixed-size data packets from said N output buffers tosaid N output ports.